The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (e.g., line) that can be created using a fabrication process) has decreased.
ICs may comprise electronic components, such as transistors, capacitors, or the like, formed on a substrate. Interconnect structures, such as conductive features (e.g., conductive lines, contacts, vias), are then formed over the electronic components to provide connections between the electronic components and to provide connections to external devices. To reduce the parasitic capacitance of the interconnect structures, the interconnect structures may be formed in low-k dielectric layers including a low-k dielectric material (e.g., a dielectric material having a k value lower than 3.8, lower than 3.0, or lower than 2.5). The width of the interconnect structures continually decreases, causing difficulties in the metal filling process forming the interconnect structures in low-k dielectric layers.
Accordingly, a method to address the above issues is needed.